1. Technical Field
This disclosure relates to semiconductor fabrication, and more particularly, to a device and method which provide a plug for a stacked capacitor having lower bitline/wordline capacitance, reduced gate conductor height and improved short yields.
2. Description of the Related Art
Stacked capacitors are known in the art as a capacitor, which extends over an active area (AA) level and a gate conductor (GC) level of a semiconductor memory device. After gate stack layers are deposited and patterned to form wordlines, cap and spacer dielectric layers are deposited to isolate the wordlines from surrounding devices to form gate structures. Gate structures are formed on the substrate in a regular line and space arrangement to isolate one word line from an adjacent word line.
Dielectric materials, such as, boro-phospor silicate glass (BPSG) are deposited over the gate structures to fill in the spaces between word lines thus insulating the gate structures.
In a separate lithographic process, a resist layer is formed over the dielectric layer and lithographically patterned. Holes are etched through the dielectric layer to open up selected gaps down to the substrate. The resist is removed, and polysilicon plugs and bitline contacts are formed by depositing polysilicon in the newly formed holes in contact with the substrate. Polysilicon is then polished from the surface of the dielectric layer. The polysilicon plug is connected to lower electrode of the stacked capacitor in subsequent steps followed by a the formation of a capacitor dielectric and upper electrode. The bitline contacts connect bitlines to the substrate.
To be able to employ a dielectric material, such as BPSG, which fills in gaps and provided a relatively planar top surface, a material, such as silicon nitride must be employed for spacers and cap dielectric layers. This permits the selective removal of BPSG to form holes for polysilicon plugs without contacting the side of the polysilicon gates. However, etching the holes in the BPSG layer subjects spacers and cap dielectric layers to an additional etch step. Although the etching is selective to silicon nitride, some silicon nitride is removed by the etch process, hence, thinning the dielectric between the gate conductor (wordlines) and plugs or bitline contacts. This often results in increased capacitive coupling between bitlines and wordlines. Also, the BPSG etch process gives rise to higher probability for short failures of, e.g., bitline contacts to wordlines and hence directly affects chip yield.
Therefore, a need exists for a device and method, which prevents thinning of spacers and cap (or liner) dielectric layers formed on gate structures. A further need exists for an improved method of forming polysilicon plugs and bitline contacts which reduces or avoids the problems of the prior art.
Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate, structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.
In alternate embodiments, the contacts may include plugs for stacked capacitors and/or bitline contacts. The conductive material may include polysilicon. The gate structures may include dielectric caps and spacers formed from an oxide and the step of removing the conductive material may include etching polysilicon selective to the oxide of the caps and spacers of the gate structures. The step of removing the conductive material may include the step of removing the conductive material in accordance with the mask to provide contacts extending above a height of the gate structures. The step of patterning a mask may include the step of patterning the mask into stripes running parallel to the gate structures over the spaces.
The step of patterning a mask may include the step of patterning the mask into a same shape as an layout area occupied by active areas in the substrate, the mask extending over the gate structures and over the spaces. The conductive material remaining in accordance with the mask may provide contacts formed having a height the same as or greater than a height of the gate structures in the spaces over the active areas.